| 摘要 |
PURPOSE:To prevent a malfunction at a high speed clock by forming a PWM output signal with a 2nd control data extracted from a latch means in response to a data set signal, a counting output data from a down--counter and the data set signal. CONSTITUTION:A data set signal line 13 is connected to the control signal input terminal of a waveform shaping circuit 5, and a part of signals of a data latch 6 is inputted to the circuit 5 through a signal line 14. Thus, the circuit 5 generates a PWM output in response to the signal on signal line 11-15 and outputs the PWM signal to a PWM signal output terminal 17 through a signal line 16. A signal line 13 is connected to a down-counter 3, an up-down control circuit 1 and a data set signal input terminal of the data latch circuit 6, and the circuit 6 receives a control data for a CPU 7 via a signal bus 18 and transmits it to the circuits 5, 1 through data buses 14, 19. Thus, no malfunction is caused at a high speed clock. |
