| 摘要 |
PURPOSE:To simplify a circuit and to shorten time for establishing synchronization by synchronizing the unit of a phase plane to be combined and the unit of a error correcting code by using an error correcting block code having a block length equal to the multiple of the number of phase planes to be combined, and synchronizing the error correcting code on the reception side. CONSTITUTION:In the case of N=2 and R=9, a transmitting data number conversion circuit 10 converts a transmitted signal 100 to a transmitting data 1 as the nine trains (R trains) of binary signals. A data conversion circuit 11 converts the data train 1 to the two pairs (N pairs) having the five trains (about R/N trains) of transmitting parallel data trains 2A and 2B. A parallel/serial conversion circuit 12 converts the data trains 2A and 2B to the five trains of transmitting serial data trains 3. While receiving this, an error correction encoding circuit 13 outputs an error correction coded serial data train 4 having the code length equal to the multiple of 2(N) synchronously with a transmission synchronizing signal 200. A multilevel modulation circuit 14 receives this and outputs a modulated signal 5. A multilevel demodulation circuit 24 inputs the modulated signal 5 and outputs the five trains of received modulated data trains 6. An error correction decoding circuit 23 decodes the data trains 6 and outputs them to a serial/parallel conversion circuit 22 together with a reception synchronizing signal 201. |
