| 摘要 |
<p>The read/write circuit comprises a data output buffer (DOB) connected through a three-state circuit (Qa, Qb) to a common data input/output terminal (I/O), and a data write-in buffer (DWB) of a dynamic type having a latching function connected between the common data input/output terminal (I/O) and data buses (DB, DB) for providng latched data to the data buses. By utilizing a rise or a fall of a write enable signal (WE) or a column address strobe signal (CAS) applied to the memory device, the three-state circuit (Qa, Qb) is set to a high impedance state, and then write data is latched into the data write-in buffer (DWB). </p> |
