| 摘要 |
<p>PURPOSE:To suppress the performance deterioration of the system at the time of error occurrence by providing a means which accepts an interruption from another processor, a means which controls the resetting functions of respective processors to a place which can be accessed by the respective processors, and a storage means which sets the interruption factor of a reset request. CONSTITUTION:A reset control unit 103 is equipped with a reset control register 201, an interruption factor setting register 202, and an interruption control register 203 and sets a value in the reset control registers 201 to reset the respective processors and release the resetting. Further, a value is set in the interruption register 203 to interrupt the respective processor and reset the interruption. Then the interruption control register 203 is used as the means which accepts the interruption from the other processor by the 1st processor unit. Consequently, the performance deterioration of the system at the time of error occurrence can be minimized.</p> |
