发明名称 |
Counter circuit with two tri-state latches |
摘要 |
A counter circuit is disclosed. The circuit has a first tri-state inverter for receiving data bits and their components. It includes a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter. It has a second tri-state inverter for receiving the data bits and their complements that is connected to the output of the first tri-state latch. It includes a second tri-state latch for receiving the data bits and their complements. The second tri-state latch is connected to the output of the second tri-state inverter. Its output is the output of the circuit, and, its output is fedback to the first tri-state inverter. Such a circuit is useful in setting an internal address of a dynamic memory device during a CBR cycle.
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申请公布号 |
US5131018(A) |
申请公布日期 |
1992.07.14 |
申请号 |
US19900560983 |
申请日期 |
1990.07.31 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MCADAMS, HUGH P.;TABACCO, PAOLO |
分类号 |
G11C8/04;H03K3/356 |
主分类号 |
G11C8/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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