| 摘要 |
A combined BAUD rate generator and digital phase locked loop (DPLL) circuit operates in either an asynchronous BAUD rate generating mode or a synchronous phase-locked mode. The combination circuit requires less circuitry than a functionally equivalent circuit with a separate BAUD rate generator and DPLL. The combination circuit comprises a count register, a period register, a decrementing/incrementing circuit, a phase adjusting circuit, and a clock option register. In a first operating mode, the combination circuit functions as a programmable BAUD rate generator which may be used for asynchronous communication applications. In a second operating mode, the combination circuit functions as both a programmable BAUD rate generator and a digital phase locked loop that may be used for synchronous communication applications and that includes an improved method for phase locking a sampling signal to an input signal. The combination circuit utilizes the same period register, count register, clock option register, and other common circuitry, during both the BAUD rate generating mode and the phase locked mode.
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