Improved data comparator for comparing plural-bit data at higher speed

摘要

An improved data comparison circuit for comparing two pieces of data having 12 bits is disclosed. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. That is, by bypassing a signal representative of the comparison result of the lower order bits through the cell circuit in which the match is detected, the delay of signal propagation which may occur in the cell circuit in which the match is detected can be prevented.