| 摘要 |
A dynamic random access memory cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for the capacitive surface of the storage-node plate of the cell capacitor. To create a DRAM array having such cells, a silicon-germanium alloy is deposited, typically via rapid thermal chemical vapor deposition, on top of a single crystalline silicon or polycrystalline silicon storage-node plate layer under conditions which favor three-dimensional growth in the form of macroscopic islanding (i.e., a high concentration of germanium in precursor gases and relatively high deposition temperature). A cell dielectric layer, which exhibits the property of bulk-limited conduction (e.g., silicon nitride), is utilized. Except for the deposition of the silicon-germanium alloy, array processing is conventional.
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