| 摘要 |
<p>PURPOSE:To prevent pulse width from being changed by affected by a temperature and a power supply voltage by providing the natural number of rotating units cascading two inverter circuits practically having the same characteristic. CONSTITUTION:Pulses can be transmitted without changing the pulse width by being passed through the several steps of buffer gates in the unit circuit cascading the two inverter circuits such as inverters 1a and 1b in this case practically having the same characteristic. The rise and fall are respectively delayed only for delay time tPHL1 and tPHL2 due to the inverter 1a. Further, the pulse is inverted by the inverter 1b and outputted while setting the pulse width to tWOUT after respectively delaying the rise and fall only for delay time tPLH2 and tPHL2 due to the inverter 1b. Therefore, the pulse width is not changed.</p> |
