| 摘要 |
<p>PURPOSE:To accurately and stably reproduce a data by decreasing a maximum phase shift by one matching of a phase of a clock with a bit synchronizing signal when a frame synchronizing signal is detected so as to switch the phase shift at bit synchronization without use of an external switching signal. CONSTITUTION:The system is provided with a clock recovery circuit 3 generating a recovered clock 300 based on a reception data 100, a CPU 9 discriminating a value of a digitized reception signal by an A/D converter 8 and detecting a period just before the reception of a frame synchronizing signal and a CPU 10 or the like detecting the frame synchronizing signal to select the mode for the bit synchronization circuit. When the frame synchronizing signal is detected by detection means 9, 10, a control means 10 applies the control of decreasing one maximum phase shift when the phase of the clock is matched with the bit synchronizing signal. Thus, it is possible to select the phase shift at bit synchronization for the reception of the bit synchronizing signal and for the reception of a data without use of an external switching signal.</p> |
