| 摘要 |
<p>An architecture for a digital-to-analog converter or an analog-to-digital converter comprises a segmented voltage divider comprising a first resistive voltage divider (11) providing a multiplicity of equal selectable voltage segments any one of which may be coupled directly across a second resistive voltage divider (19). The loading of the first resistive voltage divider by the second voltage divider is compensated by means of a controlled current source (24) which responds to one of the voltage segments to provide a current which may be coupled by way of current mirrors (29) in parallel with the second voltage divider.</p> |
