| 摘要 |
<p>An integrated circuit includes parity chains which serve as test logic. Each parity chain comprises chains of XOR gates (211, 212, 213 etc.). One input to each XOR gate after the first in a chain is connected to the output of the preceding XOR gate. The remaining inputs are connected to nodes of the main logic, thus defining test points. An error at any one of the test points is indicated in the output of the respective parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register (370) which provides a serial signature which can be analyzed to detect defects in the integrated circuit.</p> |
