发明名称 |
DIGITAL TIME BASE CORRECTOR |
摘要 |
<p>There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.</p> |
申请公布号 |
EP0158980(B1) |
申请公布日期 |
1992.07.08 |
申请号 |
EP19850104421 |
申请日期 |
1985.04.11 |
申请人 |
SONY CORPORATION |
发明人 |
SHIROTA, NORIHISA;YAMAZAKI, TAKAO;IWASE, SEIICHIRO |
分类号 |
G11B20/10;A63F7/02;G11B20/18;H03K5/00;H03K5/13;H04N5/92;H04N5/95 |
主分类号 |
G11B20/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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