| 摘要 |
<p>A delay circuit having two or more first switching transistors (51,52) connected in series between an output terminal (OUT) and a power source line (Vcc), and two or more second switching transistors (53,54) connected in series between the output terminal (OUT) and another power source line (Vss), the first and the second switching transistors operating in a complementary manner in response to an input signal (IN), one or more pairs of nodes (N5,N7) of the switching transistors being connected by one or more current paths (55) each connected to at least one capacitor (C3,C6) whereby an input signal is transmitted to the output terminal (OUT) at a specified interval defined by the capacitance of the or each capacitor.</p> |
