| 摘要 |
<p>A distributed sample scrambling system comprising scrambler and a descrambler. The scrambler includes a first shift register generator (SRG) 2 for generating scrambler SRG sequence, an exclusive OR gate 7 for generating a scrambled bitstream by adding the binary sequence to a scrambler input bitstream, and first sampling unit 2 for sampling the scrambler SRG sequence at non-uniform sampling intervals. The descrambler includes a second shift register generator 5 for generating descrambler SRG sequence, second sampling unit 4 for sampling the descrambler SRG sequence at the same sampling times, a comparator 3 for comparing the samples of descrambler SRG sequence to the samples of scrambler SRG sequence in order to determine whether said samples of both the descrambler and the scrambler are identical, a correction circuitry 6 for outputting correction signals corresponding to the comparison results of the comparator 3 to the second shift register generator 5, and an exclusive OR gate 8 for generating a descrambled bitstream by adding the descrambler SRG sequence to the scrambled bitstream of the scrambler.</p> |
