| 摘要 |
<p>PURPOSE:To decrease the number of pins by incorporating a reset circuit and discriminating between resetting which initializes a control register and resetting which holds last values according to whether a reset input is long or short. CONSTITUTION:When the reset input is asserted, an FF102 generates a clock synchronized reset signal 11 and a counter 103 is cleared to 0 with the leading edge of this signal 11. The signal is sampled thereafter with the trailing edge of a clock 6 and the counter counts up when the signal 11 is 1. When the signal 11 is 1 for a certain time, the value of the counter 103 reaches a specific value and a signal 104 becomes 1. Even when the signal 11 is >=1 for the specific time, the counter 103 stops counting and holds itself at the specific value. The signal 104 is therefore still 1. An initialization enable signal 12 is generated in synchronism with the trailing edge of the signal 11. When the assertion period of the input 7 is short and the signal does not reaches the specific period, the signal 104 is not generated and the signal 12 is not generated either.</p> |
