| 摘要 |
A computer system including: a unit (10) processing instructions containing microprogram instructions, including a first circuit (4) storing at least one instruction code group having a plurality of sub-instruction codes performing a corresponding microprogram instruction; a second circuit (1, 2, 3, 5) decoding a microprogram instruction and advancing an address of subinstructions of the microprogram instruction in response to contents of the subinstruction codes; and a third circuit (6) executing the subinstructions in response to subinstruction codes from the instruction code store circuit. The instruction code store circuit further stores a plurality of other subinstruction codes performing control of the instruction processing circuit in a debug-mode operation. The computer system also includes a control unit (40) comparing an address preset thereto and another address from the instruction decode circuit designating the subinstruction codes in the instruction code store circuit, stopping the operation of the subinstruction, and supplying at least one control data including control bits and an address designating the other subinstruction codes when the preset address coincides with the other address. The instruction execute circuit executes subinstructions of the other subinstruction codes in response to the control bits to monitor each subinstruction's operation state. The control unit may restore the stopped operation of the subinstruction when a reset signal is supplied thereto.
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