Sense amplifier with increased speed and reduced power consumption

摘要

In a programmable logic device sense amplifier, switching speed is increased and quiescent power consumption is decreased by incorporating an auxiliary high-speed circuit which assists the sense amplifier to charge the parasitic capacitance of the output node during, and for a short time after, that node's low-to-high voltage transitions. The auxiliary circuit presents a high resistance to the output node at times other than during and shortly after low-to-high transitions, and therefore does not affect the operation of the sense amplifier at these other times. The sense amplifier can be operated in single-ended bit line mode in complementary bit line mode.