| 摘要 |
PURPOSE:To reduce the number of bits of an additional code by converting a half value of a difference into a complement corresponding to a median of a maximum value and a minimum value and outputting only a valid low-order block. CONSTITUTION:A sum of a maximum value and a minimum value detected by a detection circuit 14 is extracted by an adder circuit 41 and the difference of the maximum value and the minimum value is extracted by a subtractor circuit 43 and they are respectively divided at divider circuits 48, 44 to obtain data A, B. The data A is fed to a discrimination circuit 47 as an additional code and to which term the value A is included is discriminated and the result is fed to a switch circuit 45 as a control signal. The circuit 45 is switched corresponding to the term in which the value A is included and its output signal and a picture element DT coded again by an encoder 23 are fed to a frame processing circuit 16. Moreover, bits from the circuit 44 are converted by a conversion circuit 46 as shown in a prescribed terms and the result is fed to the circuit 16, in which the data A, B for each block and the data DT coded again for each picture element are synthesized into a format signal and the result is sent from a terminal 17. Then the number of bits of the additional code is reduced. |
