Synchronised clock pulse generator with delay elements - which are series-connected for generating delayed clock pulse signals w.r.t. input delay cycle circuit

摘要

The clock pulse generator has a delay clock pulse generating circuit with numerous delay elements (211-215), generating delayed clock pulse signals (DC1-5) sequentially and serially delayed w.r.t. a basic clock pulse signal (C1) at the input (2) of the delay clock pulse generating circuit. A memory with several elements (201-205) stores a preset logic level in response to a transition in allocated basic, or delayed, clock pulse signal after application of an async. trigger signal (TR), w.r.t. the basic clock pulse signal. A clock pulse selection logic circuit (221) controlled by the memory output signal, acts on the time-proximal clock pulse signal transition. USE/ADVANTAGE - For rapid synchronisation, without use of higher frequency basic clock pulse signal.