发明名称 |
Dynamic random access memory. |
摘要 |
<p>A dynamic random access memory according to the present invention comprises a voltage stress test pad (22) to which a stress voltage is externally applied when a voltage stress test is carried out, transistors (24) which turn off when the stress voltage is not applied to the voltage stress test pad and which, when the stress voltage is applied thereto, transmit the stress voltage to more word lines than those selected in response to an external address signal in a normal operation mode, and a noise killer control circuit (38) for turning off a noise killer circuit (24) connected to a word line to which the stress voltage is applied when the voltage stress test is carried out. <IMAGE></p> |
申请公布号 |
EP0492610(A1) |
申请公布日期 |
1992.07.01 |
申请号 |
EP19910122192 |
申请日期 |
1991.12.23 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TANAKA, HIROAKI;KOYANAGI, MASARU |
分类号 |
G11C11/407;G01R31/28;G11C11/401;G11C11/404;G11C11/409;G11C29/00;G11C29/06;G11C29/34;G11C29/50;H01L21/66 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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