| 摘要 |
<p>In a pulse generator (10) an M sequence (MS1) provided from an M sequence generator (12) is delayed by a shift register (13) by 2<2> = 4 bits, and the delayed M sequence and the original M sequence are ANDed by an AND circuit (15) to create a test pulse string (TPS) of a mark ratio 1/4, which is supplied to a demultiplexer (18). A clock for operating the M sequence generator is frequency divided by a frequency divider (27) down to 1/4. An M sequence generator in a pulse error measuring device (19) is operated using the frequency-divided clock. An M sequence generated by the M sequence generator is delayed by a shift register (29) by one bit, and the delayed M sequence and the original M sequence are ANDed by an AND circuit (31) to produce a reference pulse string (RPS) of the mark ratio 1/4, which is compared with the output of the demultiplexer in a mismatch detector (23). <IMAGE></p> |
