| 摘要 |
The delay device 10 comprises an ECL gate 11 whose current source 16 and two load resistors 14, 15 are associated with a control circuit 23 producing a control voltage Vd for varying the bias current hyperbolically and a voltage Vh for maintaining the voltage on the collectors of the transistors 12 and 13 of the gate 11 constant. The delay device 10 linearly varies the delays between the input IN, IN* and output OUT, OUT* signals. The invention applies in particular to systems for transmitting digital data at very high throughput, more than 1 gigabit per second for example. <IMAGE>
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