| 摘要 |
PURPOSE:To obtain an address generation circuit which has a high probability of error correction and allows load of a CPU to be reduced by incorporating a modulator which modulates a sum of values of a column counter and a row counter and a ROM for outputting a start address in column at a signal- processing part from the modulated value. CONSTITUTION:A title item is provided with an arithmetic operation device 3 and a modulator 4 as modulation means for performing a specified modulation, a selector 11 and a ROM 5 as memory means which selects and input an output of a column counter 1, a row counter 2, or the modulator 4 and then outputs a start address in column direction which is stored according to the input, and a selector 12 and an arithmetic operation device 6 as selection arithmetic operation means for generating and outputting a RAM address signal 106 by selects and inputs an output of the column counter 1 or the row counter 2 and then obtains the sum. Therefore, addresses can be generated within the signal-processing part, thus enabling the number of steps for passing signal with the CPU to be reduced and the step for performing error correction to be increased for achieving a high error correction probability.
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