发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To compositely execute single-precision calculation on the sum of products, etc., by using a multiplier of a scale corresponding to double precision by providing a multiplicand selecting means and a means for performing partial carries and column matching of partial sums. CONSTITUTION:For example, 64-bit data are divided into two 32-bit multiplicands by means of multiplicand selecting means 5 and 6 and the divided multiplicands are respectively supplied to multiple generating means 7 and 8 on two surfaces after 32 bits of '0' are added to the higher ranks of the multiplicands. Then single-precision multiplication is performed by two times after the sum of the multiples thus generated is calculated by means of tree-like carry reservation adding means 9 and 10 on two surfaces and, after digit matching is performed on the partial carries and partial sums outputted from the means 9 and 10, the sum of products which is the final result is found by performing addition by means of two carry reservation adding means 13 and 14 and one carry propagation adding means 17. Therefore, single-precision calculation is executed on the sum of products at a high speed by adding a small amount of hardware when a large-scale multiplier is already provided for processing double-precision data at a high speed.
申请公布号 JPH04184530(A) 申请公布日期 1992.07.01
申请号 JP19900314834 申请日期 1990.11.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKANO HIROSHI
分类号 G06F7/53;G06F7/483;G06F7/52;G06F7/533 主分类号 G06F7/53
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