发明名称 |
ARITHMETIC PROCESSOR |
摘要 |
PURPOSE:To execute the operation of a block floating point with an irreducible minimum and necessary memory reading and shifting operations by obtaining an exponent correction part for a data group that indicates a shift number necessary for the normalization of plural adder/subtractor outputs in the detection of the normalized shifting number. CONSTITUTION:A barrel shifter 13 performs the shifting actions for the normalization and the matching of digits to the mantissa parts of data groups D1i and D2i in a single operation in accordance with the group D1i or D2i that has a larger exponent when both groups are normalized. Then an operation is available with an adder/subtractor 3. At the same time, a normalized shifting number detecting part 15 can obtain the exponent correcting part of a data group D3i indicating the shifting number necessary for the normalization of plural adder/subtractor outputs when these outputs are stored in a memory 1 as the mantissa part of the group D3i. Thus a block floating point can be operated just by performing the least and necessary reading and shifting operations of the memory 1 to such a data group that has the mantissa part which is not always normalized. |
申请公布号 |
JPH04184624(A) |
申请公布日期 |
1992.07.01 |
申请号 |
JP19900317295 |
申请日期 |
1990.11.20 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
ISHIKAWA TOSHIHIRO;UEDA KATSUHIKO;SUGIMURA TOSHIO |
分类号 |
G06F7/00;G06F5/01;G06F7/76 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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