Circuit and method for extracting clock signal from a serial data stream

摘要

In accordance with the invention, a circuit and a method for extracting a clock signal from a serial data stream are provided. A window pulse is generated such that transitions of a delayed version of the serial data stream occur near the center of the window pulse. A PUP signal and a PDN signal are generated having pulse widths indicative of the time at which transitions of the clock signal occur with respect to the window pulse. The PUP and PDN signals are used to generate a reference voltage to control the clock frequency. Window pulses may be generated in response to only positive transitions or to only negative transitions of the delayed serial data stream, or alternatively may be generated in response to both negative and positive transistions. The amount of delay introduced to the serial data stream may be selectively adjusted for different bit rates.