| 摘要 |
A phase lock circuit includes a control signal generator which generates a control signal changing for every frame consisting of an odd-numbered field and an even-numbered field in a reproduction mode. The control signal has a first level for a frame and a second level for a subsequent frame. The phase lock circuit further includes a first PLL circuit and a second PLL circuit. The first PLL circuit generates a first synchronizing signal which is phase-locked with a reproduced synchronizing signal for every other frame when the control signal is at the first level. The second PLL circuit generates a second synchronizing signal which is phase-locked with the reproduced synchronizing signal for every other frame when the control signal is at the second level. Furthermore, the phase lock circuit includes a select circuit which selects one of the first and second synchronizing signals supplied from the first and second PLL circuits on the basis of the control signal. The selected synchronizing signal is the synchronizing signal output from the phase lock circuit.
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