| 摘要 |
PURPOSE:To reduce the cell area by providing an Si transistor with one to two transistors and by constituting a flipflop of two P-type TFT's and two N-type TFT's. CONSTITUTION:N-type access transistors 11, 12 as transfer gates are selectively controlled by a word line WL to connect bit line pairs BL,-BL and inner nodes A, B serving as flipflop data holding nodes. P-type TFT's 13, 14 and N-type TFT's 15, 16 have reverse gates and inner nodes cross-connected to constitute a flipflop. The P-type TFT's 13, 14 and N-type TFT's 15, 16 are three- dimensionally structured by depositing polysilicon on NMOS's 11, 12. This structure makes one or two MOS transistors suffice and reduces the cell area. |
