| 摘要 |
PURPOSE:To reduce variance of output characteristics by delaying the driving timing of a field effect transistor (FET) for charge compensation. CONSTITUTION:The 2nd FET MC for compensating excessive charges due to channel accumulated charges of a 1st FET MS or charges due to feed through from a gate is driven with the signal generated by inverting a sampling pulse which is one stage behind a sampling pulse driving, for example, the MS through an inverter IVN. Namely, the MC is turned on after the MS is turned off to securely enter its off state. Consequently, even if there is slight variance in the delay time of the inverter INV connected to the gate of the MC, there is no variance in the extent of excessive charge compensation by the MC. Consequently, the variance of output characteristics is reducible. |
