发明名称 PRIORITY CONTROL SYSTEM FOR EXCHANGE
摘要 <p>PURPOSE:To supress the occurrence of a state where data is excessively accumulated in a corresponding buffer memory by abolishing a cell without accumulation when data on a bit rate exceeding a report value is inputted from a terminal and the empty area of the buffer memory in a cell buffer circuit is comparatively little. CONSTITUTION:When the bit rate of reception data exceed the report value, a bit rate detection circuit 52 adds information showing the effect to reception data so as to mark it. A header update circuit 70 sets marked reception data and reception data instructed as nonpriority data to be abolishment possible data by giving information showing abolishment is possible to a header. An accumulation judgement circuit 81 judges whether reception data is to be accumulated or not based on abolishment possible information and a data amount accumulated in the buffer memory 82. When the abolishment of data is judged, reception data is abolished. Thus, the abolishment rate of reception data with other priority is suppressed.</p>
申请公布号 JPH04179339(A) 申请公布日期 1992.06.26
申请号 JP19900306049 申请日期 1990.11.14
申请人 OKI ELECTRIC IND CO LTD 发明人 NOIRI AKIRA;ARAKAWA NOBUYA;KITAMURA TATSUHIKO;KIMURA HIROSHI
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