发明名称 QUANTISIER-SUBTRAHIERSCHALTUNG.
摘要 <p>A quantizer-subtractor circuit is provided with a input circuit for inputting an input signal and a circuit for producing a digital signal corresponding to the input signal. The quantizer-subtractor circuit contains 2n transistors. These transistors are supplied with different bias voltages by a bias circuit. A control circuit is connected to the transistors and the input circuit and controls the currents passing through the 2n transistors. A circuit produces as a subtraction output a signal corresponding to the difference between the controlled currents passing through the transistors applied with the bias voltages having odd-ordered magnitudes and the currents flowing through the transistors applied having bias voltages with the even-ordered magnitudes.</p>
申请公布号 DE3485731(D1) 申请公布日期 1992.06.25
申请号 DE19843485731 申请日期 1984.03.08
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 SUGIMOTO, YASUHIRO, KANAZAWA-KU YOKOHAMA-SHI, JP
分类号 H03M1/44;H03M1/00;(IPC1-7):H03M1/00 主分类号 H03M1/44
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