| 摘要 |
<p>A single-transistor non-volatile memory cell (50) MOS transistor (54) with a floating gate (56) and a control gate (58) using two levels of polysilicon and a tunnel dielectric that overlaps the drain area (60) wherein a tunneling of charge can take place between the drain (60) and the floating gate (56) by means of a system of applied voltages to the control gate (58) and drain (60).</p> |
