| 摘要 |
<p>PURPOSE:To synchronize even an asynchronizing signal having a shorter pulse width than a period of a clock signal by providing a hold circuit holding a 2nd asynchronizing signal to a synchronizing circuit provided with a latch circuit synchronizing a 1st asynchronizing signal with the clock signal. CONSTITUTION:When an asynchronizing signal whose pulse width is shorter than a period of a clock signal 3 is inputted to an AND circuit 10, the signal is given to a latch circuit 2, in which the signal is latched and from which a high level latch signal 4 is outputted. The signal is inputted to a latch circuit 5 through an OR circuit 11, which latches the signal 4 synchronously with the trailing of the clock signal 3 and an output signal 7 is outputted. A latch circuit 6 latches the output signal 7 synchronously with the leading of the clock signal 3 and an output signal 8 is outputted. Moreover, the latch circuit 6 outputs a signal whose polarity is opposite to that of the output signal 8 to the latch circuit 2 as a reset signal to change the latch signal 4 to a low level. Thus, even when the asynchronizing signal 1 whose pulse width is shorter than the period of the clock signal 3 is inputted to the AND circuit 10, the signal is synchronized.</p> |
