Circuit for recovery of clock-synchronised control signal - includes two identically delayed D flip=flops with open emitter output stages in wired=OR combination
摘要
Two emitter coupled logic flip flops (D1.1,D1.2) are connected (Q1 bar, D2) in series and clocked together (C1,C2) by the shift pulse (f2). The ratio of the phase regulated shift and input pulse rates (f2/f1) corresponds to the envisaged integer formatting factor. Wired OR combination of a particular output (Q2) of the second flip flop (D1.2) with an output (Q1) of the first flip flop (D1.1) establishes a useful control signal (S) for shift register operation.
申请公布号
DE4040801(A1)
申请公布日期
1992.06.25
申请号
DE19904040801
申请日期
1990.12.17
申请人
TECHNISCHE UNIVERSITAET DRESDEN, O-8027 DRESDEN, DE
发明人
SCHULZ, AXEL, O-8060 DRESDEN, DE;VETTER, TOBIAS, O-7960 LUCKAU, DE
