| 摘要 |
<p>In a memory element comprising interconnected logic gates (30a, 32a, 34a, 36a; 30b, 32b,34b, 36b) with field effect transistor metastable states are to be avoided. The device's immunity against staying in metastable states is considerably raised by coupling a supply terminal (10a; 10b) of each logic gate to a power supply voltage (16) via a base-emitter path of a bipolar transistor (14a; 14b) that has its collector coupled to the logic gate's output (8a; 8b). <IMAGE></p> |
