发明名称 MEMORY FAULT ANALYSIS DEVICE
摘要 PURPOSE:To enable an FAM size to be reduced by address compression and time for judgment for rescuing fault to be reduced by allowing a plurality of memory cells of a memory to be measured to correspond to one memory cell of a memory for analyzing fault (FAM) based on a specified rule. CONSTITUTION:Data signal from an algorithmic pattern generator is written to a corresponding region of a memory to be measured 50 which is specified for an address signal, this data is read out and is compared with an output of a generator 2 are a comparator 4, a fault signal is outputted when they do not match, and it is written into an FAM 8. In this case, a plurality of address signals are assigned as an address signal of one memory cell by an address allocation circuit 6, thus enabling a plurality of faulty memory cells to be allocated to one memory cell. This address compression allows a size of the FAM to be reduced and judgment time through the FAM for rescuing fault can be reduced.
申请公布号 JPH04177700(A) 申请公布日期 1992.06.24
申请号 JP19900306452 申请日期 1990.11.13
申请人 TOSHIBA CORP 发明人 TSUKAGOSHI HISAO
分类号 G11C29/44;G01R31/3193;G11C29/00;G11C29/40;G11C29/56 主分类号 G11C29/44
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