发明名称 |
Error detection and correction memory system. |
摘要 |
<p>Two or more memory arrays (31,32) are coupled to two or more error detection and correction (EDAC) circuits (33,34). Each memory array has a plurality of memory devices each having a plurality of outputs. The outputs of each memory are divided among the EDACs such that no more than two outputs from a single memory device are coupled to a single EDAC. <IMAGE></p> |
申请公布号 |
EP0491544(A2) |
申请公布日期 |
1992.06.24 |
申请号 |
EP19910311675 |
申请日期 |
1991.12.16 |
申请人 |
MOTOROLA INC. |
发明人 |
GRUENDER, EUGENE H., JR.;KRAFT, DOUGLAS R. |
分类号 |
G06F11/08;G06F11/10;G06F11/16;G06F12/16 |
主分类号 |
G06F11/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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