| 摘要 |
<p>PURPOSE:To attain simultaneous implementation of data series conversion and speed conversion with a sufficient operating margin by writing an input data to a memory cell section and allowing a selector section to select and extract an output of the memory cell section. CONSTITUTION:A transmission section 10 uses a write counter section 12 to frequency-divide a write clock W-CLK and to output a write pulse delayed by one bit each and writes an m-series input data Di to a memory cell section 14. A read counter section frequency-divides a read clock R-CLK to output a read delayed by one bit each thereby controlling a selector section 16. Thus, an output data Do subject to n-series conversion and speed conversion is generated and sent. A reception section 11 uses the received n-series data as an input signal Di to write it to a memory cell section 15 by using a write pulse from a write counter section 13. Then a selector section 17 is controlled with a read pulse from a read counter section 19 to select and extract an output of the cell section 15, and the output data Do subject to m-series conversion and speed conversion is obtained.</p> |
