发明名称 PLO CIRCUIT
摘要 PURPOSE:To prevent a frequency of an input clock from being changed largely by fixing an input voltage of a voltage controlled oscillator to a prescribed value when the interruption of the input clock is detected. CONSTITUTION:The circuit consists of a phase comparator 1 outputting a pulse whose width is proportional to a difference of a phase of an input clock 10 and that of a feedback clock 20, a low pass filter 2 outputting a voltage resulting from smoothing an input pulse from the phase comparator 1, an amplifier 3 having a negative feedback resistor 5 and amplifying a voltage inputted from the low pass filter 2, a voltage controlled oscillator 4 outputting the feedback clock 20 in response to an output voltage from the amplifier 3 and a detector 6 using a switch 7 to short-circuit the negative feedback resistor 5 when the input clock 10 is interrupted. When the input clock 10 is interrupted, the detector 6 closes the switch 7 thereby bringing the frequency of the output clock 10 to be almost equal to the frequency of the input clock 10 applied usually.
申请公布号 JPH04176213(A) 申请公布日期 1992.06.23
申请号 JP19900304254 申请日期 1990.11.09
申请人 NEC ENG LTD 发明人 KUDO TOSHIYUKI
分类号 H03L7/14 主分类号 H03L7/14
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