| 摘要 |
The apparatus includes a first and a second switches (6,6') for switching code data generated by a code generator (1), a first delay circuit (3) for controlling the first and the second switches and for controlling the code generator (1), a transistor (Q1) for adjusting the Baud rate, a third and a fourth switches (7,7') connected to a code detector (2), a second delay circuit (4) for controlling the third and the fourth switches, a third delay circuit (5) for delaying the output signal of the code detector (2), an AND gate (8) for operating output signals of the third delay circuit (5) and the code detector (2), and a transistor (Q2) for adjusting the Baud rate.
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