| 摘要 |
PURPOSE:To enable to execute Fermat conversion in high speed, by executing the arithmetic logic operation in one step, through the addition of several steps of gate groups modulo 2n+1. CONSTITUTION:The left input generator 1 which outputs (n+1) bit summing n-bit and suitable upper rank 1-bit while the lower n-bit is rotated with inversion by a designated number toward right or left direction, to the input of (n+1+bit from external register ACC, is provided. On the other hand, the right input generator 2 which outputs (n+1) bit summing the lower n-bit and suitable upper rank 1 bit to the input of bit from the external register MD different from the register ACC, is provided. With the modulo adder 3, to the left and right inputs in n+1 bit, the sum and n+1 bit subtracting 1 from the sum are calculated and output. Thus, Fermat conversion can be made in high speed. |
