发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RETICLE USED FOR IT
摘要 PURPOSE:To manufacture a circuit pattern composed of minute elements in an exposure region with a large resolution margin, by manufacturing a reticle arranged so that the section of a circuit block composed of minute elements put on a chip or bridging adjacent two chips on a semiconductor wafer may be the center section, or a mask formed on the basis of the reticule, and by manufacturing the circuit pattern on the semiconductor wafer using it. CONSTITUTION:A circuit pattern to form the right half of a DRAM is made in the left half of a reticle, and a circuit pattern to form the left half of the DRAM is made in the right half of the reticule, so that a scribed line by a dotted line dividing adjacent two chips may be in the vertical center. Memory arrays M1 and M3 are those which constitute right-hand side memory arrays in their original DRAMs, and in their left-hand side periphery circuit patterns corresponding to the right halves of areas C, E and D are made. Whereas, memory arrays M2 and M4 are those which constitute left-hand side memory arrays in their original DRAMs, and in their right-hand side periphery circuit patterns corresponding to the left halves of the areas C, E and D are made.
申请公布号 JPH04171860(A) 申请公布日期 1992.06.19
申请号 JP19900299431 申请日期 1990.11.05
申请人 HITACHI LTD 发明人 MATSUNO YOICHI;MIYAMOTO EIJI
分类号 G03F1/68;H01L21/027;H01L27/10 主分类号 G03F1/68
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