| 摘要 |
PURPOSE:To simplify the circuit configuration of an encoder by synchronizing a clock for sending the digital signal of analog TV signals to a transmission line to a sampling clock for A/D-converting the analog TV signals. CONSTITUTION:Analog TV signals inputted from an input terminal 1 are converted into digital signals at an A/D conversion circuit 3. At the same time, synchronizing signals are separated from the TV signals at a synchronizing separator circuit 4 and frequency-divided into M-stages at a frequency dividing circuit 5. A VCO 8 generates a clock synchronized to the separated synchronizing signals. The clock is frequency-divided into N-stages at another frequency dividing circuit 6 and the phase of the divided clock is compared with the output of the circuit 5 by means of a comparator circuit 7. After comparison, a voltage is supplied to the VCO 8 so that the VCO 8 can generate a clock synchronized to the synchronizing signals separated at the circuit 4. The clock outputted from the VCO 8 is sent to a comparator circuit 11 after the clock is frequency-divided into K-stage by means of a frequency dividing circuit 9. Then a voltage is similarly supplied to a VCO 12 so that the VCO 12 can generate a clock synchronized to that of the VCO 8. A multiplex circuit 13 multiplexes the outputs of the circuit 3 and VCO 12. |
