| 摘要 |
PURPOSE:To fix a single rounding position for omission of a complicated rounding position detector circuit and to perform a floating point arithmetic operation at a high speed by applying the normalization processing and then the rounding processing to the arithmetic result of the mantissa of two floating point numbers whose digits are matched with each other. CONSTITUTION:The number of leading zero bits of the mantissa arithmetic result are counted by a leading zero detector means 11, and the mantissa arithmetic result is shifted to the left by a left shifter 12 by an extent equal to the count value of the leading zero bits. The output of the shifter 13 is inputted to a rounding adder 13. The rounding positions are fixed to the single one owing to a fact that the output of the shifter 12 is normalized. As a result, a rounding position deciding circuit can be omitted and the hardware quantity of the adder 13 itself can be reduced. Thus the rounding processing is carried out at a high speed. |
