Circuitry generating data clock signals for magnetic disc store - uses PLL with ring oscillator based upon delay stages

摘要

A combined PLL is used for the generation of both write (WCK) and read (RCK) control pulses. The unit has a v.c.o. circuit (3) with a ring of delay stages (41-4n), each of which has an adjustable valve (deltat). The output of the last stage is fed back to form the ring oscillator. The delay stages connect to a selector circuit (9) to generate the read clock signal which is also fed to a phase detector (10). A further phase detector (7) provides the input to the oscillator. ADVANTAGE - Common circuit for read and write pulses.