Data signal stop bit removing circuit - uses phase regulating loop with phase comparator matching frequency of write and read clock with read clock phase adjustment

摘要

The stop bit removal circuit uses a phase regulating loop with a phase comparator for matching the read clock frequency to the write clock frequency. A clock gap is inserted in the read clock after a given number of stop bits. A correction circuit alters the phase of the read clock by an amount equal to 360 degrees divided by a number which is 1 greater than the number of phase variations between each 2 clock gaps. Pref. the phase position is altered for each received stop bit. ADVANTAGE - Reduces signal jitter.