| 摘要 |
PURPOSE:To secure an S/P converting function after frame variation by inputting the inputs of a data input terminal and a frame input terminal to a DMX circuit and a shift register through flip-flop circuits respectively. CONSTITUTION:When the high-frame signal with one-clock width which is inputted to the frame signal input terminal 2 is inputted deviating from every 8n clocks, the shift register (SFT) 9 is reset with the frame signal. The S/P timing control input signal of the DMX circuit 5 is therefore inputted at intervals of eight clocks in synchronism with a new frame signal. Even if output pulses of the SFT 9 contains a pulse other than pulses of every eight clocks owing to a noise, etc., the high-level frame signal with one-clock width is inputted. Consequently, the SFT 9 is reset and then outputs pulses at intervals of eight clocks synchronized with the input frame signal. |
