| 摘要 |
Virtual addresses from multiple address spaces are translated to real addresses in main memory by generating for each virtual address an address space identifier (AID) identifying its address space. Then, the virtual address and its AID are used to obtain the real address. The address spaces include a shared address space, from which the processor can provide a virtual address at any time, as well as switched address spaces, from one of which the processor can provide a virtual address at a given time. A dedicated VLSI map cache translates by keeping the most recently accessed mapping entries, each of which associates a virtual address and its AID with a real address. If the virtual address is from the shared address space, the map cache uses the shared AID, but if not, the map cache uses the current switched AID for the processor providing the virtual address. Each processor in a shared memory multiprocessor may execute a map cache fault handling routine from a bypass area in memory when it encounters a map cache miss. The map cache obtains a bypass area real address algorithmically based on the virtual address, so that a map cache miss cannot occur in accessing the bypass area. The bypass area also includes a hashed map table, which includes only entries for pages loaded into main memory and all entries for those pages. Therefore, a map table fault occurs only when a page fault occurs, and is handled by another routine stored in the bypass area. The map cache includes features that must be in hardware for reasons of speed, while the bypass area contents provide the remaining functionality in software which can be modified easily to enhance function or performance.
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