发明名称 Trinary check trit generator, latch, comparator and multiplexer
摘要 A method and apparatus for performing data error detection and correction is disclosed for multi-level logic and in particular, three-level trinary logic of levels 0, 1, 2. A source of trinary data supplies individual pieces of data (trits of 0, or 1, or 2) in multiple trit groups (trytes) to two separate check trit generators which generate unique check trits for each tryte input. The check trits from the two check trit generators are compared to form syndrome trits which are used to control an error detection function. For single errors per tryte a data correction function is activated to increment or decrement the incorrect data through a multiplexer. Multiple errors or no error conditions are indicated, but do not gate the data correction function.
申请公布号 US5122688(A) 申请公布日期 1992.06.16
申请号 US19900518617 申请日期 1990.05.03
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GRIMES, DWIGHT W.
分类号 G06F11/10;H03M5/16;H03M5/20;H03M13/00 主分类号 G06F11/10
代理机构 代理人
主权项
地址